`timescale 1ns / 1ns

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:11:13 11/14/2011
// Design Name:   main
// Module Name:   /home/uraj/opt/Xilinx/13.1/test/test_all.v
// Project Name:  test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_all;

	// Inputs
	reg [31:0] din;
	reg clk;
	reg rst;

	// Outputs
	wire [31:0] dout;

	// Instantiate the Unit Under Test (UUT)
	main uut (
		.din(din), 
		.clk(clk), 
		.rst(rst), 
		.dout(dout)
	);

	initial begin
		// Initialize Inputs
		din = 0;
		clk = 0;
		rst = 1;

		// Wait 100 ns for global reset to finish
		#15;
        rst = 0;
		// Add stimulus here

	end
    always begin
        #5;
        clk = ~clk;
    end
    always begin
        #10;
        din = din + 1;
    end
endmodule

